16.5 DESIGN TECHNIQUES
16.5.1 State Diagrams
The block logic method was introduced in chapter 8 to implement state diagrams using MCR blocks. A better implementation of this method is possible using subroutines in program files. The ladder logic for each state will be put in separate subroutines.
Consider the state diagram in Figure 246. This state diagram shows three states with four transitions. There is a potential conflict between transitions A and C.
Figure 246 A State Diagram
The main program for the state diagram is shown in Figure 247. This program is stored in the MainProgram so that it is run by default. The first rung in the program resets the states so that the first scan state is on, while the other states are turned off. The following logic will call the subroutine for each state. The logic that uses the current state is placed in the main program. It is also possible to put this logic in the state subroutines.
Figure 247 The Main Program for the State Diagram (Program File 2)
The ladder logic for each of the state subroutines is shown in Figure 248. These blocks of logic examine the transitions and change states as required. Note that state STB includes logic to give state C higher priority, by blocking A when C is active.
Figure 248 Subroutines for the States
The arrangement of the subroutines in Figure 247 and Figure 248 could experience problems with racing conditions. For example, if STA is active, and both B and C are true at the same time the main program would jump to subroutine 3 where STB would be turned on. then the main program would jump to subroutine 4 where STC would be turned on. For the output logic STB would never have been on. If this problem might occur, the state diagram can be modified to slow down these race conditions. Figure 249 shows a technique that blocks race conditions by blocking a transition out of a state until the transition into a state is finished. The solution may not always be appropriate.
Figure 249 A Modified State Diagram to Prevent Racing
Another solution is to force the transition to wait for one scan as shown in Figure 250 for state STA. A wait bit is used to indicate when a delay of at least one scan has occurred since the transition out of the state B became true. The wait bit is set by having the exit transition B true. The B3/0-STA will turn off the wait B3/10-wait when the transition to state B3/1-STB has occurred. If the wait was not turned off, it would still be on the next time we return to this state.
Figure 250 Subroutines for State STA to Prevent Racing
